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July 2007
HYB18M 256320 C F- 6 / 7 . 5 HYE18M 256320 C F- 6 / 7 . 5 HYB18M 256160 C F- 6 / 7 . 5 HYE18M 256160 C F- 6 / 7 . 5
DRAMs for Mobile Applications 256-Mbit Mobile-RAM
Internet Data Sheet
Rev.1.44
Internet Data Sheet
HY[B/E]18M256[16/32]0CF 256-Mbit DDR Mobile-RAM
HYB18M256320CF-6/7.5, HYE18M256320CF-6/7.5, HYB18M256160CF-6/7.5 , HYE18M256160CF-6/7.5 Revision History: Rev.1.44, 2007-07 Page All 55, 56 24 25 All All Subjects (major changes since last revision) Adapted Internet Edition Editorial changes Updated Figure 44 for 60-ball PG-VFBGA-60-4 (x16) Updated Figure 45 for 90-ball PG-VFBGA-90-3 (x32) New Qimonda Template. see Change List Rev. 1.41
Previous Revision:Rev.1.43, 2007-04
Previous Revision:Rev.1.42, 2007-03
Previous Revision:Rev.1.40, 2006-06
We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: techdoc@qimonda.com
qag_techdoc_rev400 / 3.2 QAG / 2006-08-07 06262007-JK8G-48BV
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Internet Data Sheet
HY[B/E]18M256[16/32]0CF 256-Mbit DDR Mobile-RAM
1
1.1
Overview
Features
* Organization: - 4 banks x 4 Mbit x 16, 1 KB page size - 4 banks x 2 Mbit x 32, 2 KB page size * Double-data-rate architecture: two data transfers per clock cycle * Bidirectional data strobe (DQS) is transmitted / received with data; to be used in capturing data at the receiver * DQS is edge-aligned with data for READs and center-aligned with data for WRITEs * Differential clock input (CK / CK) * Commands entered on positive CK edge; data and mask data are referenced to both edges of DQS * Four internal banks for concurrent operation * Programmable CAS latency: 2 and 3 * Programmable burst length: 2, 4, 8, 16 and full page * Programmable drive strength: full, 1/2, 1/4 and 1/8 * Auto refresh and self refresh modes * Refresh cycles: - 8192 refresh cycles / 64ms (x16) - 4096 refresh cycles / 64ms (x32) * Auto precharge * Commercial (-0C to +70C) and Extended (-25C to +85C) operating temperature ranges * Package: - x16: 60-ball PG-VFBGA-60-4 10.0 x 10.5 x 1.0 mm - x32: 90-ball PG-VFBGA-60-3 10.0 x 12.5 x 1.0 mm * RoHS Compliant Products1) Power Saving Features * * * * * * Low supply voltages: VDD = 1.70 V - 1.95 V, VDDQ = 1.70 V - 1.95 V Optimized operating (IDD0, IDD4), self refresh (IDD6) and standby currents (IDD2, IDD3) DDR I/O scheme with no DLL Programmable Partial Array Self Refresh (PASR) Temperature Compensated Self-Refresh (TCSR), controlled by on-chip temperature sensor Clock Stop, Power-Down and Deep Power-Down modes
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury, lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.
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Internet Data Sheet
HY[B/E]18M256[16/32]0CF 256-Mbit DDR Mobile-RAM
TABLE 1
Performance
Part Number Speed Code Clock Frequency (fCKmax) Access Time (tACmax) CL = 3 CL = 2 -6 166 83 5.5 - 7.5 133 83 6.0 Unit MHz MHz ns
TABLE 2
Memory Addressing Scheme
Item Banks Rows Columns Addresses BA0, BA1 A0 - A12 (x16) A0 - A11 (x32) A0 - A8
TABLE 3
Ordering Information
Type1) Package Description 166/133 MHz 4 Banks x 2 Mbit x 32 Low Power DDR SDRAM 166/133 MHz 4 Banks x 4 Mbit x 16 Low Power DDR SDRAM 166/133 MHz 4 Banks x 2 Mbit x 32 Low Power DDR SDRAM 166/133 MHz 4 Banks x 4 Mbit x 16 Low Power DDR SDRAM Standard Temperature Range HYB18M256320CF-6/7.5 90-ball PG-VFBGA-60-3 HYB18M256160CF-6/7.5 60-ball PG-VFBGA-60-4 Extended Temperature Range HYE18M256320CF-6/7.5 90-ball PG-VFBGA-60-3 HYE18M256160CF-6/7.5 60-ball PG-VFBGA-60-4
1) HY[B/E]: Designator for memory products (HYB: Standard temp. range, HYE: Extended temp. range) 18M: 1.8V DDR Mobile-RAM 256: 256 MBit density 16/32: 16 or 32 bit interface width C: die revisionF: green product -6 / -7.5: speed grades (min. clock cycle time)
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Internet Data Sheet
HY[B/E]18M256[16/32]0CF 256-Mbit DDR Mobile-RAM
1.2
Pin Configuration
FIGURE 1
Standard Ballout 256-MBit x16 DDR Mobile-RAM (Top View 60-ball)
FIGURE 2
Standard Ballout 256-MBit x32 DDR Mobile-RAM (Top View 90-ball)
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Internet Data Sheet
HY[B/E]18M256[16/32]0CF 256-Mbit DDR Mobile-RAM
1.3
Description
The HY[B/E]18M256[16/32]0CF is a high-speed CMOS, dynamic random-access memory containing 268,435,456 bits. It is internally configured as a quad-bank DRAM. The HY[B/E]18M256[16/32]0CF uses a double-data-rate architecture to achieve high-speed operation. The double-data-rate architecture is essentially a 2n pre fetch architecture, with an interface designed to transfer two or four data words per clock cycle at the I/O pins. A single READ or WRITE access for the HY[B/E]18M256[16/32]0CF consists of a single 2n-bit wide, one clock cycle data transfer at the internal DRAM core and two corresponding n-bit wide, one-half clock cycle data transfers at the I/O pins. The HY[B/E]18M256[16/32]0CF is especially designed for mobile applications. It operates from a 1.8V power supply. Power consumption in self refresh mode is drastically reduced by an On-Chip Temperature Sensor (OCTS); it can further be reduced by using the programmable Partial Array Self Refresh (PASR). A conventional data-retaining Power-Down (PD) mode is available as well as a non-data-retaining Deep Power-Down (DPD) mode. For further power-savings the clock may be stopped during idle periods. The HY[B/E]18M256[16/32]0CF is housed in a BGA package. It is available in Standard (-0C to +70C) and Extended (-25C to +85C) temperature ranges.
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Internet Data Sheet
HY[B/E]18M256[16/32]0CF 256-Mbit DDR Mobile-RAM
1.4
Pin Definition and Description
TABLE 4
Pin Description
Ball CK, CK CKE Type Input Input Detailed Function Clock: CK and CK are differential clock inputs. All address and control inputs are sampled on crossing of the positive edge of CK and negative edge of CK. Clock Enable: CKE HIGH activates and CKE LOW deactivates internal clock signals, and device input buffers and output drivers. Taking CKE LOW provides precharge power-down and self refresh operation (all banks idle), or active power-down (row active in any bank). CKE must be maintained HIGH throughout read and write accesses. Input buffers, excluding CK, CK and CKE are disabled during power-down. Input buffers, excluding CKE are disabled during self refresh. Chip Select: All commands are masked when CS is registered HIGH. CS provides for external bank selection on systems with multiple banks. CS is considered part of the command code Command Inputs: RAS, CAS and WE (along with CS) define the command being entered. Data Inputs/Output: Bi-directional data bus
CS RAS, CAS, WE DQ0 - DQ15 (x16)DQ0 DQ31 (x32)
Input Input I/O
LDQS, UDQS I/O (x16)DQS0 DQS3 (x32)
Data Strobe: output with read data, input with write data. Edge-aligned with read data, centered with write data. Used to capture write data. For x16 LDQS corresponds to the data on DQ0 - DQ7; UDQS to the data on DQ8 - DQ15. For x32 DQS0 corresponds to the data on DQ0 - DQ7, DQS1 to the data on DQ8 - DQ15, DQS2 to the data on DQ16 - DQ23, DQS3 to the data on DQ24 - DQ31. Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH coincident with that input data during a WRITE access. DM is sampled on both edges of DQS. Although DM pins are input only, the DM loading matches the DQ and DQS loading. For x16 LDM corresponds to the data on DQ0 - DQ7; UDM to the data on DQ8 - DQ15. For x32 DM0 corresponds to the data on DQ0 - DQ7, DM1 to the data on DQ8 - DQ15, DM2 to the data on DQ16 - DQ23, DM3 to the data on DQ24 - DQ31. Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVATE, READ, WRITE or PRECHARGE command is being applied. BA0, BA1 also determine which mode register is to be loaded during a MODE REGISTER SET command (MRS or EMRS). Address Inputs: Provide the row address for ACTIVE commands and the column address and Auto Precharge bit for READ/WRITE commands, to select one location out of the memory array in the respective bank. A10 (=AP) is sampled during a precharge command to determine whether the PRECHARGE applies to one bank (A10=LOW) or all banks (A10=HIGH). If only one bank is to be precharged, the bank is selected by BA0 and BA1. The address inputs also provide the op-code during a MODE REGISTER SET command. I/O Power Supply: Isolated power for DQ output buffers for improved noise immunity: VDDQ = 1.70 V - 1.95 V I/O Ground Power Supply: Power for the core logic and input buffers, VDD = 1.70 V - 1.95 V Ground No Connect
LDM, UDM (x16)DM0 DM3 (x32)
Input
BA0, BA1
Input
A0 - A12 (x16) Input A0 - A11 (x32)
VDDQ VSSQ VDD VSS
N.C.
Supply Supply Supply Supply -
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Internet Data Sheet
HY[B/E]18M256[16/32]0CF 256-Mbit DDR Mobile-RAM
2
Functional Description
The DDR Mobile-RAM is a high-speed CMOS, dynamic random-access memory containing 268,435,456 bits. It is internally configured as a quad-bank DRAM. READ and WRITE accesses to the DDR Mobile-RAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA0, BA1 select the banks, A0 - A12 (x16)/A0 - A11 (x32), select the row). The address bits registered coincident with the READ or WRITE command are used to select the starting column location for the burst access. Prior to normal operation, the DDR Mobile-RAM must be initialized. The following sections provide detailed information covering device initialization, register definition, command description and device operation.
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Internet Data Sheet
HY[B/E]18M256[16/32]0CF 256-Mbit DDR Mobile-RAM
2.1
Register Definition
2.1.1
Mode Register
The Mode Register is used to define the specific mode of operation of the DDR Mobile-RAM. This definition includes the selection of a burst length (bits A0-A2), a burst type (bit A3) and a CAS latency (bits A4-A6). The Mode Register is programmed via the MODE REGISTER SET command (with BA0 = 0 and BA1 = 0) and will retain the stored information until it is programmed again or the device loses power. The Mode Register must be loaded when all banks are idle, and the controller must wait the specified time before initiating any subsequent operation. Violating either of these requirements results in unspecified operation. Reserved states should not be used, as unknown operation or incompatibility with future versions may result. Full page bursts wrap within the page if the boundary is reached. Please note that full page bursts do not self-terminate; this implies that full-page read or write bursts with Auto Precharge are not legal commands. Full page burst has to start from an even column address. Mode Register Definition (BA[1:0] = 00B)
Field CL
Bits [6:4]
Type w
Description CAS Latency 010B CL 2 011B CL 3 Note: All other bit combinations are RESERVED. Burst Type 0B BT Sequential 1B BT Interleaved Burst Length 001B BL 2 010B BL 4 011B BL 8 100B BL 16 111B BL Full page (Sequential burst type only) Note: All other bit combinations are RESERVED. Reserved address bits Note: Amax = A12 for x16, A11 for x32
BT
3
w
BL
[2:0]
w
A
[Amax:7]
w
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Internet Data Sheet
HY[B/E]18M256[16/32]0CF 256-Mbit DDR Mobile-RAM
2.1.2
Extended Mode Register
The Extended Mode Register controls additional low power features of the device. These include the Partial Array Self Refresh (PASR), the Temperature Compensated Self Refresh (TCSR) and the drive strength selection for the DQs. The Extended Mode Register is programmed via the MODE REGISTER SET command (with BA0 = 0 and BA1 = 1) and will retain the stored information until it is programmed again or the device loses power. The Extended Mode Register must be loaded when all banks are idle, and the controller must wait the specified time before initiating any subsequent operation. Violating either of these requirements result in unspecified operation. Address bits A0 A2 specify the Partial Array Self Refresh (PASR) and bits A5 - A6 the Drive Strength, while bits A7 - Amax shall be written to zero. Bits A3 and A4 are "don't care" (see below). Reserved states should not be used, as unknown operation or incompatibility with future versions may result. Mode Register Definition (BA[1:0] = 00B)
Field DS
Bits [6:5]
Type w
Description Selectable Drive Strength 00B DS Full Drive Strength 01B DS Half Drive Strength 10B DS Quarter Drive Strength 11B DS 1/8 Drive Strength Temperature Compensated Self Refresh XXB TCSR Superseded by on-chip temperature sensor (see text) Partial Array Self Refresh 000B PASR all banks 001B PASR half array (BA1 = 0) 010B PASR quarter array (BA1 = BA0 = 0) Note: All other bit combinations are RESERVED. Reserved address bits Note: Amax = A12 for x16, A11 for x32
TCSR
[4:3]
w w
PASR [2:0]
A
[Amax:7]
w
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Internet Data Sheet
HY[B/E]18M256[16/32]0CF 256-Mbit DDR Mobile-RAM
2.2
Function Truth Tables
TABLE 5
Truth Table - CKE
CKEn-1 L CKEn L Current State Power-Down Self Refresh Deep Power-Down L H Power-Down Self Refresh Deep Power-Down H L All Banks Idle Bank(s) Active All Banks Idle All Banks Idle H
1) 2) 3) 4) 5) 6)
Command X X X DESELECT or NOP DESELECT or NOP X DESELECT or NOP DESELECT or NOP AUTO REFRESH BURST TERMINATE
Action Maintain Power-Down Maintain Self Refresh Maintain Deep Power-Down Exit Power-Down Exit Self Refresh Exit Deep Power-Down Enter Precharge Power-Down Enter Active Power-Down Enter Self Refresh Enter Deep Power-Down
Note
1)2)3)4) 1)2)3)4) 1)2)3)4) 1)2)3)4)5) 1)2)3)4)5) 1)2)3)4)6) 1)2)3)4) 1)2)3)4) 1)2)3)4) 1)2)3)4) 1)2)3)4)
H
See Table 6 and Table 7
CKEn is the logic state of CKE at clock edge n; CKEn-1 was the state of CKE at the previous clock edge. Current state is the state immediately prior to clock edge n. COMMAND n is the command registered at clock edge n; ACTION n is a result of COMMAND n. All states and sequences not shown are illegal or reserved. DESELECT or NOP commands should be issued on any clock edges occurring during tXP or tXSR period. Exit from DEEP POWER DOWN requires the same command sequence as for power-up initialization.
TABLE 6
Current State Bank n - Command to Bank n
Current State Any Idle CS H L L L L Row Active L L L Read (AutoPrecharge Disabled) L L L L RAS X H L L L H H L H H L H CAS X H H L L L L H L L H H WE X H H H L H L L H L L L Command / Action DESELECT (NOP / continue previous operation) NO OPERATION (NOP / continue previous operation) ACTIVE (select and activate row) AUTO REFRESH MODE REGISTER SET READ (select column and start Read burst) WRITE (select column and start Write burst) PRECHARGE (Deactivate row in bank or banks) READ (truncate Read and start new Read burst) WRITE (truncate Read and start new Write burst) PRECHARGE (truncate Read and start Precharge) BURST TERMINATE Note
1)2)3)4)5)6) 1)2)3)4)5)6) 1)2)3)4)5)6) 1)2)3)4)5)6)7) 1)2)3)4)5)6)7) 1)2)3)4)5)6)8) 1)2)3)4)5)6)8) 1)2)3)4)5)6)9) 1)2)3)4)5)6)8) 1)2)3)4)5)6)8)10) 1)2)3)4)5)6)9) 1)2)3)4)5)6)11)
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HY[B/E]18M256[16/32]0CF 256-Mbit DDR Mobile-RAM
Current State Write (AutoPrecharge Disabled)
CS L L L
RAS H H L
CAS L L H
WE H L L
Command / Action READ (truncate Write and start Read burst) WRITE (truncate Write and start Write burst)
Note
1)2)3)4)5)6)8)12) 1)2)3)4)5)6)8)
POWER-DOWN or SELF REFRESH). 2) This table is bank-specific, except where noted, i.e., the current state is for a specific bank and the commands shown are those allowed to be issued to that bank when in that state. Exceptions are covered in the notes below. 3) Current state definitions:Idle: The bank has been precharged, and tRP has been met.Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts / accesses and no register accesses are in progress.Read: A read burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.Write: A write burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated. 4) The following states must not be interrupted by a command issued to the same bank. DESELECT or NOP commands, or allowable commands to the other bank should be issued on any clock edge occurring during these states. Allowable commands to the other bank are determined by its current state and according to Table 7.Precharging: Starts with registration of a PRECHARGE command and ends when tRP is met. Once tRP is met, the bank is in the "idle" state.Row Activating: Starts with registration of an ACTIVE command and ends when tRCD is met. Once tRCD is met, the bank is in the "row active" state.Read with AP enabled: Starts with registration of a READ command with Auto Precharge enabled and ends when tRP has been met. Once tRP is met, the bank is in the idle state.Write with AP enabled: Starts with registration of a WRITE command with Auto Precharge enabled and ends when tRP has been met. Once tRP is met, the bank is in the idle state. 5) The following states must not be interrupted by any executable command; DESELECT or NOP commands must be applied on each positive clock edge during these states.Refreshing: Starts with registration of an AUTO REFRESH command and ends when tRC is met. Once tRC is met, the DDR Mobile-RAM is in the "all banks idle" state.Accessing Mode Register: Starts with registration of a MODE REGISTER SET command and ends when tMRD has been met. Once tMRD is met, the DDR Mobile-RAM is in the "all banks idle" state.Precharging All: Starts with registration of a PRECHARGE ALL command and ends when tRP is met. Once tRP is met, all banks are in the idle state. 6) All states and sequences not shown are illegal or reserved. 7) Not bank-specific; requires that all banks are idle and no bursts are in progress. 8) Reads or Writes listed in the Command/Action column include Reads or Writes with Auto Precharge enabled and Reads or Writes with Auto Precharge disabled. 9) May or may not be bank-specific; if multiple banks are to be precharged, each must be in a valid state for precharging. 10) A WRITE command may be applied after the completion of the Read burst; otherwise, a BURST TERMINATE command must be used to end the Read burst prior to issuing a WRITE command. 11) Not bank-specific; BURST TERMINATE affects the most recent Read burst, regardless of bank. 12) Requires appropriate DM masking.
1)2)3)4)5)6)9)12) PRECHARGE (truncate Write burst, start Precharge) 1) This table applies when CKEn-1 was HIGH and CKEn is HIGH (see Table 7) and after tXP or tXSR has been met (if the previous state was
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HY[B/E]18M256[16/32]0CF 256-Mbit DDR Mobile-RAM
TABLE 7
Current State Bank n - Command to Bank m (different bank)
Current State Any Idle Row Activating, Active, or Precharging CS H L X L L L L Read (AutoPrecharge Disabled) L L L L Write (AutoPrecharge Disabled) L L L L Read(with Auto- L Precharge) L L L Write(with Auto- L Precharge) L L L RAS X H X L H H L L H H L L H H L L H H L L H H L CAS X H X H L L H H L L H H L L H H L L H H L L H WE X H X H H L L H H L L H H L L H H L L H H L L Command / Action DESELECT (NOP / continue previous operation) NO OPERATION (NOP / continue previous operation) Any command otherwise allowed to bank m ACTIVE (select and activate row) READ (select column and start Read burst) WRITE (select column and start Write burst) PRECHARGE (Deactivate row in bank or banks) ACTIVE (select and activate row) READ (truncate Read and start new Read burst) WRITE (truncate Read and start Write burst) PRECHARGE (Deactivate row in bank or banks) ACTIVE (select and activate row) READ (truncate Write and start Read burst) WRITE (truncate Write and start new Write burst) PRECHARGE (Deactivate row in bank or banks) ACTIVE (select and activate row) READ (truncate Read and start new Read burst) WRITE (truncate Read and start Write burst) PRECHARGE (deactivate row in bank or banks) ACTIVE (select and activate row) READ (truncate Write and start Read burst) WRITE (truncate Write and start new Write burst) Note
1)2)3)4)5)6) 1)2)3)4)5)6) 1)2)3)4)5)6) 1)2)3)4)5)6) 1)2)3)4)5)6)7) 1)2)3)4)5)6)7) 1)2)3)4)5)6) 1)2)3)4)5)6) 1)2)3)4)5)6)7) 1)2)3)4)5)6)7)8) 1)2)3)4)5)6) 1)2)3)4)5)6) 1)2)3)4)5)6)7)9) 1)2)3)4)5)6)7) 1)2)3)4)5)6) 1)2)3)4)5)6) 1)2)3)4)5)6)7) 1)2)3)4)5)6)7)8) 1)2)3)4)5)6) 1)2)3)4)5)6) 1)2)3)4)5)6)7) 1)2)3)4)5)6)7)
power-down or self refresh). 2) This table describes alternate bank operation, except where noted, i.e., the current state is for bank n and the commands shown are those allowed to be issued to bank m (assuming that bank m is in such a state that the given command is allowable). Exceptions are covered in the notes below. 3) Current state definitions:Idle: The bank has been precharged, and tRP has been met.Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts / accesses and no register accesses are in progress.Read: A read burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.Write: A write burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.Read with AP enabled: Starts with registration of a READ command with Auto Precharge enabled and ends when tRP has been met. Once tRP is met, the bank is in the idle state.Write with AP enabled: Starts with registration of a WRITE command with Auto Precharge enabled and ends when tRP has been met. Once tRP is met, the bank is in the idle state. 4) AUTO REFRESH, SELF REFRESH and MODE REGISTER SET commands may only be issued when all banks are idle. 5) A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current state only. 6) All states and sequences not shown are illegal or reserved. 7) Reads or Writes listed in the Command/Action column include Reads or Writes with Auto Precharge enabled and Reads or Writes with Auto Precharge disabled. 8) A WRITE command may be applied after the completion of the Read burst; otherwise, a BURST TERMINATE command must be used to end the Read burst prior to issuing a WRITE command. 9) Requires appropriate DM masking.
1)2)3)4)5)6) PRECHARGE (Deactivate row in bank or banks) 1) This table applies when CKEn-1 was HIGH and CKEn is HIGH (see Table 7) and after tXP or tXSR has been met (if the previous state was
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HY[B/E]18M256[16/32]0CF 256-Mbit DDR Mobile-RAM
3
3.1
Electrical Characteristics
Operating Conditions
TABLE 8
Absolute Maximum Ratings
Parameter Symbol Min. Power Supply Voltage Power Supply Voltage for Output Buffer Input Voltage Output Voltage Operation Case Temperature Storage Temperature Power Dissipation Short Circuit Output Current Extended Values Max. 2.7 2.7 V V V V C C W mA - - - - - - - - Unit Note
VDD VDDQ VIN VOUT TC TSTG PD IOUT
-0.3 -0.3 -0.3 -0.3 -25 -55 - -
VDDQ + 0.3 VDDQ + 0.3
+85 +150 0.7 50
Attention: Stresses above those listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.Maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit.
TABLE 9
Pin Capacitances
Parameter Symbol Min. Input capacitance: CK, CK Input capacitance: all other input-only pins Input/output capacitance: DQ, DQS, DM Values Max. 5.0 3.5 4.5 pF pF pF - - - Unit Note1)
2)3)
CI1 CI2 CIO
2.5 1.5 2.0
1) These values are not subject to production test but verified by device characterization. 2) Input capacitance is measured according to JEP147 procedure for measuring capacitance using a vector network analyzer. VDD, VDDQ are applied and all other pins (except the pin under test) are floating. DQ's should be in high impedance state. This may be achieved by pulling CKE to low level. 3) Although DM is an input-only pin, it's input capacitance models the input capacitance of the DQ and DQS pins.
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HY[B/E]18M256[16/32]0CF 256-Mbit DDR Mobile-RAM
TABLE 10
Electrical Characteristics
Parameter Symbol Min. Power Supply Voltage Power Supply Voltage for DQ Output Buffer Input leakage current Output leakage current Input high voltage Input low voltage Clock Inputs (CK, CK) DC input voltage DC input differential voltage AC input differential voltage AC differential cross point voltage Data Inputs (DQ, DM, DQS) DC input high voltage DC input low voltage AC input high voltage AC input low voltage Data Outputs (DQ, DQS) Output high voltage (IOH = -0.1 mA)
1) 2) 3) 4)
Values Max. 1.95 1.95 1.0 1.0
Unit
Note1)2)
VDD VDDQ IIL IOL VIH VIL VIN VID(DC) VID(AC) VIX VIHD(DC) VILD(DC) VIHD(AC) VILD(AC) VOH VOL
1.70 1.70 -1.0 -1.0 0.8 x VDDQ -0.3 -0.3 0.4 x VDDQ 0.6 x VDDQ 0.4 x VDDQ 0.7 x VDDQ -0.3 0.8 x VDDQ -0.3 0.9 x VDDQ
V V A V V V V V V V V V V V
- - - - - - -
3) 3) 4)
Address and Command Inputs (BA, BA1, CKE, CS, RAS, CAS, WE)
VDDQ + 0.3 0.2 x VDDQ VDDQ + 0.3 VDDQ + 0.6 VDDQ + 0.6 0.6 x VDDQ VDDQ + 0.3 0.3 x VDDQ VDDQ + 0.3 0.2 x VDDQ
-
- - - - - -
Output low voltage (IOL = 0.1 mA) - 0.1 x VDDQ V 0 C TC 70 C (comm.); -25C TC 85 C (ext.)All voltages referenced to VSS. VSS and VSSQ must be at same potential.
See Table 12 and Figure 4 for overshoot and undershoot definition.
VID is the magnitude of the difference between the input level on CK and the input level on CK. The value of VIX is expected to be equal to 0.5 x VDDQ and must track variations in the DC level.
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HY[B/E]18M256[16/32]0CF 256-Mbit DDR Mobile-RAM
3.2
AC Characteristics
TABLE 11
AC Characteristics
Parameter Symbol Min. DQ output access time from CK/CK DQS output access time from CK/CK Clock high-level width Clock low-level width Clock half period Clock cycle time DQ and DM input Setup time DQ and DM input hold time DQ and DM input pulse width Address and control input Setup time Address and control input hold time fast slew rate slow slew rate fast slew rate slow slew rate CL = 3 CL = 2 fast slew rate slow slew rate Fast slew rate Slow slew rate -6 Max. 5.5 5.5 0.55 0.55 - - - - - - - - - - - - - 5.5 0.5 0.55 1.25 0.6 0.6 1.1 - - - - - 0.6 - Min. 2.5 2.5 0.45 0.45 7.5 12 0.75 0.85 0.75 0.85 1.7 1.3 1.5 1.3 1.5 3.0 1.0 - - - 0.75 0.4 0.4 0.9 0.2 0.2 2 0 0.25 0.4 0.25 6.0 6.0 0.55 0.55 - - - - - - - - - - - - - 6.0 0.6 0.75 1.25 0.6 0.6 1.1 - - - - - 0.6 - ns ns ns ns ns ns ns ns ns ns ns
9)10)11) 9)10)12) 9)10)12) 9)10)13) 13) 12)14)15) 13)15)16) 12)15)16) 13)15)16) 14) 16) 17) 17) 8) 8)
- 7.5 Max.
Unit Note
1)2)3)4)
tAC tDQSCK tCH tCL tHP tCK tDS tDH tDIPW tIS tIH tIPW tLZ tHZ tDQSQ tQH tQHS tDQSS tDQSH tDQSL tDSC tDSS tDSH tMRD tWPRES tWPREH tWPST tWPRE
2.0 2.0 0.45 0.45 6 12 0.6 0.7 0.6 0.7 1.5 1.1 1.3 1.1 1.3 2.6 1.0 - - - 0.75 0.4 0.4 0.9 0.2 0.2 2 0 0.25 0.4 0.25
ns ns
5)6) 5)6)
tCK tCK
ns ns
- -
7)8)
min(tCL, tCH)
min(tCL, tCH)
Address and control input pulse width DQ & DQS low-impedance time from CK/CK DQ & DQS high-impedance time from CK/CK DQS - DQ skew DQ / DQS output hold time from DQS Data hold skew factor Write command to 1st DQS latching transition DQS input high-level width DQS input low-level width DQS input cycle time DQS falling edge to CK setup time DQS falling edge hold time from CK MODE REGISTER SET command period Write preamble setup time Write preamble hold time Write postamble Write preamble
tHP-tQHS -
tHP-tQHS -
tCK tCK tCK tCK tCK tCK tCK
ns
- - - - - - -
18)
tCK tCK tCK
-
19)
-
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Internet Data Sheet
HY[B/E]18M256[16/32]0CF 256-Mbit DDR Mobile-RAM
Parameter
Symbol Min.
-6 Max. 1.1 - 0.6 70k - - - - - - - - - - - 64 7.8 (x 16) 15.6 (x32) Min. 0.9 0.5 0.4 45 67 75 22.5 1 22.5 15 15 1 120 2 - -
- 7.5 Max. 1.1 1.1 0.6 70k - - - - - - - - - - 64 7.8 (x 16) 15.6 (x32)
Unit Note
1)2)3)4)
Read preamble Read postamble
CL = 3 CL = 2
tRPRE tRPST tRAS tRC tRFC tRCD tCCD tRP tRRD tWR tDAL tWTR tXSR tXP tCKE tREF tREFI
0.9 - 0.4 42 60 72 18 1 18 12 15 1 120
tCK tCK
ns ns ns ns
20)
-
21) 22) 22)
ACTIVE to PRECHARGE command period ACTIVE to ACTIVE command period AUTO REFRESH to ACTIVE/AUTO REFRESH command period ACTIVE to READ or WRITE delay Col address to col address delay PRECHARGE command period ACTIVE bank A to ACTIVE bank B delay WRITE recovery time Auto precharge write recovery + precharge time Internal write to Read command delay Self refresh exit to next valid command delay Exit power down delay CKE minimum low time Refresh period Average periodic refresh interval
22)
tCK
ns ns ns
22) 22) 22) 22) 23) 22)
(tWR/tCK) + (tRP/tCK)
tCK tCK
ns ns
tCK + tIS
2 - -
tCK + tIS -
- -
24)
tCK
ms s
1) 0 C TC 70 C (comm.); -25C TC 85 C (ext.);VDD = 1.70 V - 1.95 V, VDDQ = 1.70 V - 1.95 V. All voltages referenced to VSS. 2) All parameters assume proper device initialization. 3) The CK/CK input reference level (for timing referenced to CK/CK) is the point at which CK and CK; the input reference level for signals other than CK/CK is VDDQ/2. 4) All AC timing characteristics assume an input slew rate of 1.0 V/ns. 5) The output timing reference level is VDDQ/2. 6) Parameters tAC and tQH are specified for full drive strength and a reference load see Figure 3. This circuit is not intended to be either a precise representation of the typical system environment nor a depiction of the actual load presented by a production tester. For half drive strength with a nominal load of 10pF parameters tAC and tQH are expected to be in the same range. However, these parameters are not subject to production test but are estimated by device characterization. Use of IBIS or other simulation tools for system validation is suggested. 7) Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can be greater than the minimum specification limits for tCL and tCH). 8) tQH = tHP - tQHS, where tHP = minimum half clock period for any given cycle and is defined by clock high or clock low (tCL, tCH). tQHS accounts for 1) the pulse duration distortion of on-chip clock circuits; and 2) the worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the next transition, both of which are, separately, due to data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers. 9) DQ, DM and DQS input slew rate is measured between VILD(DC) and VIHD(AC) (rising) or VIHD(DC) and VILD(AC) (falling). 10) DQ, DM and DQS input slew rate is specified to prevent double clocking of data and preserve setup and hold times. Signal transitions through the DC region must be monotonic. 11) Input slew rate 1.0 V/ns. 12) Input slew rate 0.5V/ns and < 1.0 V/ns. 13) These parameters guarantee device timing. They are verified by device characterization but are not subject to production test. 14) The transition time for address and command inputs is measured between VIH and VIL. 15) A CK/CK differential slew rate of 2.0 V/ns is assumed for this parameter. 16) tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
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Internet Data Sheet
HY[B/E]18M256[16/32]0CF 256-Mbit DDR Mobile-RAM
17) tDQSQ consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers for any given cycle. 18) The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge. A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS. 19) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system performance (bus turnaround) will degrade accordingly. 20) A low level on DQS may be maintained during High-Z states (DQS drivers disabled) by adding a weak pull-down element in the system. It is recommended to turn off the weak pull-down element during read and write bursts (DQS drivers enabled). 21) These parameters account for the number of clock cycles and depend on the operating frequency, as follows:no. of clock cycles = specified delay / clock period; round to the next higher integer. 22) tDAL = (tWR / tCK) + (tRP / tCK): for each of the terms above, if not already an integer, round to the next higher integer. 23) tWTR is also referred to as tCDLR 24) A maximum of eight AUTOREFRESH commands can be posted to the DDR Mobile-RAM device, meaning that the maximum absolute interval between any Refresh command and the next Refresh command is 8 * tREFI.
FIGURE 3
Measurement with Reference Load
TABLE 12
AC Overshoot / Undershoot Specification
Parameter Maximum peak amplitude allowed for overshoot Maximum peak amplitude allowed for undershoot Maximum overshoot area above VDD Maximum undershoot area below VSS Max. 0.5 0.5 3.0 3.0 Unit V V V-ns V-ns Note - - - -
FIGURE 4
AC Overshoot and Undershoot Definition
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Internet Data Sheet
HY[B/E]18M256[16/32]0CF 256-Mbit DDR Mobile-RAM
3.3
Operating Currents
TABLE 13
Maximum Operating Currents
Parameter & Test Conditions Symbol -6 Operating one bank active-precharge current: Values - 7.5 40 (x16) 55 (x32) mA Unit Note
1)2)3)4)5)
tRC = tRCmin; tCK = tCKmin; CKE is HIGH; CS is HIGH between valid
IDD0
45 (x16) 60 (x32)
commands; address inputs are SWITCHING; data bus inputs are STABLE 0.7 0.7 mA
IDD2P Precharge power-down standby current: All banks idle, CKE is LOW; CS is HIGH, tCK = tCKmin; address and control inputs are SWITCHING; data bus inputs are STABLE
Precharge power-down standby current with clock stop: IDD2PS All banks idle, CKE is LOW; CS is HIGH, CK = LOW, CK = HIGH; address and control inputs are SWITCHING; data bus inputs are STABLE
0.3
0.3
mA
IDD2N Precharge non power-down standby current: All banks idle, CKE is HIGH; CS is HIGH, tCK = tCKmin;address and control inputs are SWITCHING; data bus inputs are STABLE
Precharge non power-down standby current with clock stop: IDD2NS All banks idle, CKE is HIGH; CS is HIGH, CK = LOW, CK = HIGH;address and control inputs are SWITCHING; data bus inputs are STABLE Active power-down standby current: One bank active, CKE is LOW; CS is HIGH, tCK = tCKmin; address and control inputs are SWITCHING; data bus inputs are STABLE
15
15
mA
8
8
mA
IDD3P
2.0
2.0
mA
IDD3PS Active power-down standby current with clock stop: One bank active, CKE is LOW; CS is HIGH, CK = LOW, CK = HIGH; address and control inputs are SWITCHING; data bus inputs are STABLE
Active non power-down standby current: One bank active, CKE is HIGH; CS is HIGH, tCK = tCKmin;address and control inputs are SWITCHING; data bus inputs are STABLE Active non power-down standby current with clock stop: One bank active, CKE is HIGH; CS is HIGH, CK = LOW, CK = HIGH;address and control inputs are SWITCHING; data bus inputs are STABLE
1.5
1.5
mA
IDD3N
25
23
mA
IDD3NS
20
20
mA
IDD4R Operating burst read current: One bank active; BL = 4; CL = 3; tCK = tCKmin; continuous read bursts; IOUT = 0 mAaddress inputs are SWITCHING; 50% data change each burst transfer
Operating burst write current: One bank active; BL = 4; tCK = tCKmin; continuous write bursts; address inputs are SWITCHING; 50% data change each burst transfer Auto-Refresh current: SWITCHING; data bus inputs are STABLE
115 (x16) 140 (x32)
90 (x16) 110 (x32)
mA
IDD4W
110 (x16) 115 (x32) 75 (x16) 120 (x32)
85 (x16) 90 (x32) 70 (x16) 110 (x32)
mA
tRC = tRFCmin; tCK = tCKmin; burst refresh; address and control inputs are
IDD5
mA
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Internet Data Sheet
HY[B/E]18M256[16/32]0CF 256-Mbit DDR Mobile-RAM
Parameter & Test Conditions
Symbol -6
Values - 7.5
Unit
Note
1)2)3)4)5)
Self refresh current: CKE is LOW; CK = LOW, CK = HIGH; address and control inputs are STABLE; data bus inputs are STABLE
IDD6
See Table 14
A
6) Deep Power Down current IDD8 10 10 A 1) 0 C TC 70 C (comm.); -25C TC 85 C (ext.); VDD = 1.70 V - 1.95 V, VDDQ = 1.70 V - 1.95 V.Recommended Operating Conditions
unless otherwise noted 2) IDD specifications are tested after the device is properly initialized and measured at 133 MHz for -7.5 speed grade, and 166 MHz for -6 speed grade. 3) Input slew rate is 1.0 V/ns. 4) Definitions for IDD:LOW is defined as VIN 0.1 * VDDQ;HIGH is defined as VIN 0.9 * VDDQ;STABLE is defined as inputs stable at a HIGH or LOW level;SWITCHING is defined as:- address and command: inputs changing between HIGH and LOW once per two clock cycles;- data bus inputs: DQ changing between HIGH and LOW once per clock cycle; DM and DQS are STABLE 5) All parameters are measured with no output loads. 6) Value shown as typical and measured at 25 C.
TABLE 14
Self Refresh Currents
Parameter & Test Conditions Max. Temperature Symbol Values Typ. Self refresh mode, Full array (PASR = 000) Self refresh mode, Half array (PASR = 001) Self refresh mode, Quarter array (PASR = 010) 85 C 40 C 85 C 40 C 85 C 40 C Max. 400 - 340 - 310 - A
1)2)
Units
Note
IDD6
275 145 210 115 185 100
1) -25 C TJ 85 C (ext.); VDD = VDDQ = 1.70V to 1.95V 2) For commercial temperature range part (HYB), the max value indicated for 85 C applies to 70 C
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Internet Data Sheet
HY[B/E]18M256[16/32]0CF 256-Mbit DDR Mobile-RAM
4
Package Outlines
FIGURE 5
60-ball PG-VFBGA-60-4 (x16)
Notes 1. 2. 3. 4. 5. 6. Solder ball attach fiducial (SBA) Middle of package edges Package orientation mark A1 Bad unit marking (BUM) Tolerances regarding ISO 2768-mK Dimensions in mm
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Internet Data Sheet
HY[B/E]18M256[16/32]0CF 256-Mbit DDR Mobile-RAM
FIGURE 6
90-ball PG-VFBGA-60-3 (x32)
Notes 1. 2. 3. 4. 5. 6. Solder ball attach fiducial (SBA) Middle of package edges Package orientation mark A1 Bad unit marking (BUM) Tolerances regarding ISO 2768-mK Dimensions in mm
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Internet Data Sheet
HY[B/E]18M256[16/32]0CF 256-Mbit DDR Mobile-RAM
List of Figures
Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Standard Ballout 256-MBit x16 DDR Mobile-RAM (Top View 60-ball) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Standard Ballout 256-MBit x32 DDR Mobile-RAM (Top View 90-ball) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Measurement with Reference Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 AC Overshoot and Undershoot Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 60-ball PG-VFBGA-60-4 (x16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 90-ball PG-VFBGA-60-3 (x32) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
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Internet Data Sheet
HY[B/E]18M256[16/32]0CF 256-Mbit DDR Mobile-RAM
List of Tables
Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Memory Addressing Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Truth Table - CKE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Current State Bank n - Command to Bank n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Current State Bank n - Command to Bank m (different bank) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Pin Capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 AC Overshoot / Undershoot Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Maximum Operating Currents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Self Refresh Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
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Doc_Preliminary Internet Data Sheet,
HY[B/E]18M256[16/32]0CF 256-Mbit DDR Mobile-RAM
Table of Contents
1 1.1 1.2 1.3 1.4 2 2.1 2.1.1 2.1.2 2.2 3 3.1 3.2 3.3 4 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Definition and Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3 5 6 7
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Extended Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Function Truth Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 14 16 19
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
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Internet Data Sheet
Edition 2007-07 Published by Qimonda AG Gustav-Heinemann-Ring 212 D-81739 Munchen, Germany (c) Qimonda AG 2007. All Rights Reserved. Legal Disclaimer The information given in this Internet Data Sheet shall in no event be regarded as a guarantee of conditions or characteristics ("Beschaffenheitsgarantie"). With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Qimonda hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Qimonda Office. Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Qimonda Office. Under no circumstances may the Qimonda product as referred to in this Internet Data Sheet be used in 1. Any applications that are intended for military usage (including but not limited to weaponry), or 2. Any applications, devices or systems which are safety critical or serve the purpose of supporting, maintaining, sustaining or protecting human life (such applications, devices and systems collectively referred to as "Critical Systems"), if a) A failure of the Qimonda product can reasonable be expected to - directly or indirectly (i) Have a detrimental effect on such Critical Systems in terms of reliability, effectiveness or safety; or (ii) Cause the failure of such Critical Systems; or b) A failure or malfunction of such Critical Systems can reasonably be expected to - directly or indirectly (i) Endanger the health or the life of the user of such Critical Systems or any other person; or (ii) Otherwise cause material damages (including but not limited to death, bodily injury or significant damages to property, whether tangible or intangible). www.qimonda.com

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